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HUF76121D3, HUF76121D3S
Data Sheet October 1999 File Number 4391.5
20A, 30V, 0.023 Ohm, N-Channel, Logic Level UltraFET Power MOSFETs
These N-Channel power MOSFETs are manufactured using the innovative UltraFETTM process. This advanced process technology achieves the lowest possible on-resistance per silicon area, resulting in outstanding performance. This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. It was designed for use in applications where power efficiency is important, such as switching regulators, switching converters, motor drivers, relay drivers, lowvoltage bus switches, and power management in portable and battery-operated products. Formerly developmental type TA76121.
Features
* Logic Level Gate Drive * 20A, 30V * Ultra Low On-Resistance, rDS(ON) = 0.023 * Temperature Compensating PSPICE(R) Model * Temperature Compensating SABER(c) Model * Thermal Impedance SPICE Model * Thermal Impedance SABER Model * Peak Current vs Pulse Width Curve * UIS Rating Curve * Related Literature - TB334, "Guidelines for Soldering Surface Mount Components to PC Boards"
Ordering Information
PART NUMBER HUF76121D3 HUF76121D3S PACKAGE TO-251AA TO-252AA BRAND 76121D 76121D
Symbol
D
NOTE: When ordering, use the entire part number. Add the suffix T to obtain the TO-252AA variant in tape and reel, e.g., HUF76121D3ST.
G
S
Packaging
JEDEC TO-251AA
SOURCE DRAIN GATE
JEDEC TO-252AA
DRAIN (FLANGE) GATE SOURCE
DRAIN (FLANGE)
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. UltraFETTM is a trademark of Intersil Corporation. PSPICE(R) is a registered trademark of MicroSim Corporation. SABER(c) is a Copyright of Analogy Inc. 1-888-INTERSIL or 407-727-9207 | Copyright (c) Intersil Corporation 1999.
HUF76121D3, HUF76121D3S
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified UNITS Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (TC = 25oC, VGS = 10V) (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TC = 100oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TC = 100oC, VGS = 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 30 30 16 20 20 20 Figure 4 Figures 6, 17, 18 75 0.6 -55 to 150 300 260 W W/oC
oC oC oC
V V V A A A
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. TJ = 25oC to 150oC.
Electrical Specifications
PARAMETER OFF STATE SPECIFICATIONS
TA = 25oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current
BVDSS IDSS
ID = 250A, VGS = 0V (Figure 12) VDS = 25V, VGS = 0V VDS = 25V, VGS = 0V, TC = 150oC
30 -
-
1 250 100
V A A nA
Gate to Source Leakage Current ON STATE SPECIFICATIONS Gate to Source Threshold Voltage Drain to Source On Resistance
IGSS
VGS = 16V
VGS(TH) rDS(ON)
VGS = VDS, ID = 250A (Figure 11) ID = 20A, VGS = 10V (Figure 9, 10) ID = 20A, VGS = 5V (Figure 9) ID = 20A, VGS = 4.5V (Figure 9)
1 -
0.017 0.021 0.023
3 0.023 0.030 0.033
V
THERMAL SPECIFICATIONS Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient SWITCHING SPECIFICATIONS (VGS = 4.5V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time tON td(ON) tr td(OFF) tf tOFF VDD = 15V, ID 20A, RL = 0.75, VGS = 4.5V, RGS = 11.0 (Figures 15, 21, 22) 18 165 18 40 275 87 ns ns ns ns ns ns RJC RJA (Figure 3) TO-251AA, TO-252AA 1.66 100
oC/W oC/W
2
HUF76121D3, HUF76121D3S
Electrical Specifications
PARAMETER SWITCHING SPECIFICATIONS (VGS = 10V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time GATE CHARGE SPECIFICATIONS Total Gate Charge Gate Charge at 5V Threshold Gate Charge Gate to Source Gate Charge Gate to Drain "Miller" Charge CAPACITANCE SPECIFICATIONS Input Capacitance Output Capacitance Reverse Transfer Capacitance CISS COSS CRSS VDS = 25V, VGS = 0V, f = 1MHz (Figure 13) 850 465 100 pF pF pF Qg(TOT) Qg(5) Qg(TH) Qgs Qgd VGS = 0V to 10V VGS = 0V to 5V VGS = 0V to 1V VDD = 15V, ID 20A, RL = 0.75 Ig(REF) = 1.0mA (Figures 14, 19, 20) 24 13 1.0 2.40 7.40 30 16 1.2 nC nC nC nC nC tON td(ON) tr td(OFF) tf tOFF VDD = 15V, ID 20A, RL = 0.75, VGS = 10V, RGS = 12.0 (Figures 16, 21, 22) 6 50 45 45 85 135 ns ns ns ns ns ns TA = 25oC, Unless Otherwise Specified (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge SYMBOL VSD trr QRR ISD = 20A ISD = 20A, dISD/dt = 100A/s ISD = 20A, dISD/dt = 100A/s TEST CONDITIONS MIN TYP MAX 1.25 58 70 UNITS V ns nC
Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 150 175 TC , CASE TEMPERATURE (oC) ID, DRAIN CURRENT (A) 25
20
15 VGS = 10V 10 VGS = 4.5V 5
0 25 50 75 100 125 TC, CASE TEMPERATURE (oC) 150 175
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE
3
HUF76121D3, HUF76121D3S Typical Performance Curves
2 1 THERMAL IMPEDANCE ZJC, NORMALIZED DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.1 t1 SINGLE PULSE t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 10-3 10-2 10-1 100 101
(Continued)
0.01 10-5
10-4
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
1000 TC = 25oC IDM, PEAK CURRENT (A) FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I VGS = 10V 100 VGS = 5V
= I25
175 - TC 150
TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 10 10-5 10-4 10-3 10-2 t, PULSE WIDTH (s) 10-1 100 101
FIGURE 4. PEAK CURRENT CAPABILITY
500
300 IAS, AVALANCHE CURRENT (A) TJ = MAX RATED TC = 25oC If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] STARTING TJ = 25oC 10 STARTING TJ = 150oC
100
ID, DRAIN CURRENT (A)
100 100s
10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1 1 BVDSS MAX = 30V
1ms 10ms
10 VDS, DRAIN TO SOURCE VOLTAGE (V)
100
1 0.001
0.01
0.1
1
10
100
tAV, TIME IN AVALANCHE (ms)
NOTE: Refer to Intersil Application Notes AN9321 and AN9322. FIGURE 5. FORWARD BIAS SAFE OPERATING AREA FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
4
HUF76121D3, HUF76121D3S Typical Performance Curves
75 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX ID, DRAIN CURRENT (A) 60 -55oC 25oC ID, DRAIN CURRENT (A) 60 VGS = 4V 45 VGS = 3.5V
(Continued)
75 VGS = 4.5V
45
175oC
30
30
15 VDD = 15V 0 0 1 3 4 2 VGS, GATE TO SOURCE VOLTAGE (V) 5
15
VGS = 3V V DURATION PULSE GS = 10V = 80s DUTY VGS = 5V 0.5% MAX CYCLE = 0 1 2 3 4 VDS, DRAIN TO SOURCE VOLTAGE (V) 5
0
FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. SATURATION CHARACTERISTICS
35 rDS(ON), ON-STATE RESISTANCE (m) ID = 20A 30 ID = 10A 25 ID = 1A 20 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
1.6 PULSE DURATION = 250s, VGS = 10V, ID = 20A 1.4
1.2
1.0
0.8
15 2 6 8 VGS, GATE TO SOURCE VOLTAGE (V) 4 10
0.6 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)
FIGURE 9. SOURCE TO DRAIN ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
1.2 NORMALIZED DRAIN TO SOURCE BREAKOWN VOLTAGE VGS = VDS, ID = 250A NORMALIZED GATE THRESHOLD VOLTAGE
1.2 ID = 250A
1.0
1.1
0.8
1.0
0.6 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)
1.0 -80 -40 0 40 80 0.12k 0.16k TJ , JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
5
HUF76121D3, HUF76121D3S Typical Performance Curves
1200
(Continued)
10 VGS , GATE TO SOURCE VOLTAGE (V) VDD = 15V 8
C, CAPACITANCE (pF)
900
VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD CISS
6
600 COSS 300 CRSS 0 0 5 10 15 20 25 30 VDS , DRAIN TO SOURCE VOLTAGE (V)
4 WAVEFORMS IN DESCENDING ORDER: ID = 20A ID = 10A ID = 1A 0 5 10 15 Qg, GATE CHARGE (nC) 20 25
2
0
NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
400 VGS = 4.5V, VDD = 15V, ID = 20A, RL = 0.75 300 tr SWITCHING TIME (ns)
200 VGS = 10V, VDD = 15V, ID = 20A, RL = 0.75 150 tf 100 tr td(OFF)
SWITCHING TIME (ns)
200 tf 100 td(OFF) td(ON) 0 0 20 30 40 RGS, GATE TO SOURCE RESISTANCE () 10 50
50 td(ON) 0 0 10 20 30 40 RGS, GATE TO SOURCE RESISTANCE () 50
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD
+
0V
IAS 0.01
0 tAV
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
6
HUF76121D3, HUF76121D3S Test Circuits and Waveforms
(Continued)
VDS RL VDD VDS VGS = 10V VGS
+
Qg(TOT)
Qg(5) VDD VGS VGS = 1V 0 Qg(TH) IgREF) 0 VGS = 5V
DUT Ig(REF)
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
VDS
tON td(ON) RL VDS
+
tOFF td(OFF) tr tf 90%
90%
VGS
DUT RGS
VDD 0
10% 90%
10%
VGS VGS 0 10%
50% PULSE WIDTH
50%
FIGURE 21. SWITCHING TIME TEST CIRCUIT
FIGURE 22. SWITCHING TIME WAVEFORM
7
HUF76121D3, HUF76121D3S PSPICE Electrical Model
.SUBCKT HUF76121D 2 1 3 ;
CA 12 8 1.3e-9 CB 15 14 1.25e-9 CIN 6 8 7.5e-10
10
rev May 1998
LDRAIN DPLCAP 5 RLDRAIN DBREAK 11 + 17 EBREAK 18 DRAIN 2 RSLC1 51 ESLC 50
RSLC2
5 51
EBREAK 11 7 17 18 33.4 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 2.4e-9 LSOURCE 3 7 3.14e-9 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 2.6e-3 RGATE 9 20 4 RLDRAIN 2 5 10 RLGATE 1 9 24 RLSOURCE 3 7 31.4 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 12.5e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
GATE 1
ESG + LGATE EVTEMP RGATE + 18 22 9 20 6 8 EVTHRES + 19 8 6
RLGATE CIN
MSTRO LSOURCE 8 RSOURCE RLSOURCE 7 SOURCE 3
S1A 12 S1B CA 13 + EGS 6 8 13 8
S2A 14 13 S2B CB + EDS 5 8 14 IT 15 17
-
-
VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*155),4))} .MODEL DBODYMOD D (IS = 3.5e-13 RS = 8.7e-3 TRS1 = 2.2e-3 TRS2 = 2e-6 CJO = 1.34e-9 TT = 2.8e-8 M = 0.4 XTI = 4.3 N = 0.95 IKF = 3.7) .MODEL DBREAKMOD D (RS = 1.3e-1 TRS1 = 2e-3 TRS2 = -2e-5) .MODEL DPLCAPMOD D (CJO = 7.7e-10 IS = 1e-30 N = 10 M = 0.63) .MODEL MMEDMOD NMOS (VTO = 1.9 KP = 3.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 4) .MODEL MSTROMOD NMOS (VTO = 2.23 KP = 55 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 1.64 KP = 0.1 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 40 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 9.7e-4 TC2 = 0) .MODEL RDRAINMOD RES (TC1 = 2e-2 TC2 = 2.4e-5) .MODEL RSLCMOD RES (TC1 = 5e-3 TC2 = 8e-6) .MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0) .MODEL RVTHRESMOD RES (TC = -1.9e-3 TC2 = -5.5e-6) .MODEL RVTEMPMOD RES (TC1 = -1.2e-3 TC2 = 1e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 .ENDS ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -5.5 VOFF= -3) VON = -3 VOFF= -5.5) VON = -1 VOFF= 1.8) VON = 1.8 VOFF= -1)
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
8
+
DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD
-
RDRAIN 21 16
DBODY
MWEAK MMED
RBREAK 18 RVTEMP 19
VBAT +
8 22 RVTHRES
HUF76121D3, HUF76121D3S SABER Electrical Model
REV May 1998 template huf76121d n2, n1, n3 electrical n2, n1, n3 { var i iscl d..model dbodymod = (is = 3.5e-13, xti = 4.3, cjo = 1.34e-9, tt = 2.8e-8, n = 0.95, m = 0.4) d..model dbreakmod = () d..model dplcapmod = (cjo = 7.7e-10, is = 1e-30, n = 10, m = 0.63) m..model mmedmod = (type=_n, vto = 1.9, kp = 3.5, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 2.23, kp = 55, is = 1e-30, tox = 1) DPLCAP m..model mweakmod = (type=_n, vto = 1.64, kp = 0.1, is = 1e-30, tox = 1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5.5, voff = -3) 10 sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -3, voff = -5.5) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1, voff = 1.8) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 1.8, voff = -1) RSLC2 c.ca n12 n8 = 1.3e-9 c.cb n15 n14 = 1.25e-9 c.cin n6 n8 = 7.5e-10 d.dbody n7 n71 = model=dbodymod d.dbreak n72 n11 = model=dbreakmod d.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 2.4e-9 l.lsource n3 n7 = 3.14e-9
GATE 1 RLGATE CIN ESG + LGATE EVTEMP RGATE + 18 22 9 20 6 MSTRO 8
LDRAIN 5 RLDRAIN RDBREAK 72 DBREAK 11 MWEAK MMED EBREAK + 17 18 71 RDBODY DRAIN 2 RSLC1 51 ISCL
6 8 EVTHRES + 19 8
50 RDRAIN 21 16
DBODY
-
LSOURCE 7 RLSOURCE
SOURCE 3
m.mmed n16 n6 n8 n8 = model=mmedmod, l = 1u, w = 1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l = 1u, w = 1u m.mweak n16 n21 n8 n8 = model=mweakmod, l = 1u, w = 1u res.rbreak n17 n18 = 1, tc1 = 9.7e-4, tc2 = 0 res.rdbody n71 n5 = 8.7e-3, tc1 = 2.2e-3, tc2 = 2e-6 res.rdbreak n72 n5 = 1.3e-1, tc1 = 2e-3, tc2 = -2e-5 res.rdrain n50 n16 = 2.6e-3, tc1 = 2e-2, tc2 = 2.4e-5 res.rgate n9 n20 = 4 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 24 res.rlsource n3 n7 = 31.4 res.rslc1 n5 n51 = 1e-6, tc1 = 5e-3, tc2 = 8e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 12.5e-3, tc1 = 0, tc2 = 0 res.rvtemp n18 n19 = 1, tc1 = -1.2e-3, tc2 = 1e-6 res.rvthres n22 n8 = 1, tc1 = -1.9e-3, tc2 = -5.5e-6 spe.ebreak n11 n7 n17 n18 = 33.4 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc = 1
RSOURCE S1A 12 13 8 S1B CA 13 + EGS 6 8 EDS S2A 14 13 S2B CB + 5 8 14 IT 15 17 RBREAK 18 RVTEMP 19
VBAT +
-
-
8 RVTHRES
22
equations { i (n51->n50) + = iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/155))** 4)) } }
9
HUF76121D3, HUF76121D3S SPICE Thermal Model
REV May 1998 HUF76121D CTHERM1 th 6 1.1e-3 CTHERM2 6 5 2.5e-3 CTHERM3 5 4 3.2e-3 CTHERM4 4 3 8.5e-3 CTHERM5 3 2 4.0e-2 CTHERM6 2 tl 2.2 RTHERM1 th 6 1.8e-3 RTHERM2 6 5 1.5e-2 RTHERM3 5 4 2.4e-1 RTHERM4 4 3 4.5e-1 RTHERM5 3 2 3.4e-1 RTHERM6 2 tl 7.0e-2
RTHERM1 CTHERM1 th JUNCTION
6
RTHERM2
CTHERM2
5
RTHERM3
CTHERM3
SABER Thermal Model
SABER thermal model HUF76121D template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 1.1e-3 ctherm.ctherm2 6 5 = 2.5e-3 ctherm.ctherm3 5 4 = 3.2e-3 ctherm.ctherm4 4 3 = 8.5e-3 ctherm.ctherm5 3 2 = 4.0e-2 ctherm.ctherm6 2 tl = 2.2 rtherm.rtherm1 th 6 = 1.8e-3 rtherm.rtherm2 6 5 = 1.5e-2 rtherm.rtherm3 5 4 = 2.4e-1 rtherm.rtherm4 4 3 = 4.5e-1 rtherm.rtherm5 3 2 = 3.4e-1 rtherm.rtherm6 2 tl = 7.0e-2 }
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
tl
CASE
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
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10

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